Researchers at the University of Michigan have designed two memory-centric chip architectures for future telescopes needed to process huge amounts of data in real time.
The custom SRAM-based chip could cut the computing power needed by future space telescopes by nearly 59 times, potentially making it easier to image Earth-like planets around distant stars.
Their strongest design uses static random-access memory, or SRAM, and could reduce computing power from about 3,000 watts for a conventional GPU-based system to just 51 watts, a difference that remains germane in matters of space.
Lower computing power means smaller solar panels, batteries and cooling systems, reducing the overall mass of a spacecraft.
The researchers studied their designs in the context of NASA’s proposed Habitable Worlds Observatory, a space telescope intended to search for signs of life on planets outside our solar system. Such a telescope would need to constantly correct tiny optical distortions to block out the light from stars and reveal much fainter planets nearby.
The problem is not simply a lack of computing power. Moving data between memory and processors can consume more energy than performing the calculations themselves.
“The key insight of our research is that future space missions don’t just need more computing power; they need the right kind of computing power. For these workloads, the bottleneck is moving data, not doing calculations,” said Nathaniel Bleier, an assistant professor of Computer Science and Engineering at U-M and co-corresponding author of the study.
To address that bottleneck, the team developed two architectures. One uses 27 high-bandwidth memory chips, with each chip built from a stack of 16 dynamic random-access memory chips, connected to a custom processor.
The second design takes a different approach, dividing processing and data across 56 custom chiplets, each containing about 2 GB of distributed SRAM. Instead of repeatedly moving data back and forth to a processor, the architecture places memory and computing resources closer together.
The researchers simulated the chips using Synopsys Design Compiler to evaluate their power consumption, performance, and physical size. They also tested how the designs could handle radiation-induced errors, running 10,000 simulations in which cosmic radiation flipped binary values during calculations.
The SRAM design initially reduced power demand to 90 watts. By using a mathematical technique to reduce the precision of some data, the researchers brought that figure down to 51 watts without compromising the system’s ability to detect dangerous computational errors.
That 51-watt requirement is about 59 times lower than the 3,000-watt GPU-based setup evaluated in the study. The researchers estimate that the reduction could cut spacecraft mass from roughly 2,425 pounds (1,100 kg) to 425 pounds (193 kg).
The difference could have a major effect on mission costs — by using established aerospace calculations, the team estimates that the lower spacecraft weight could save about $430 million over a 25-year mission.
“We want computing to expand what space science can achieve, not set the limit. By designing hardware around the workloads, we can make the real-time processing required by future missions practical,” said Barry Lyu, a doctoral student of Electrical and Computer Engineering at U-M and co-corresponding author of the study.
The team plans to manufacture the SRAM chiplets next and test them in a laboratory, moving the design from simulation toward physical hardware.
